1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, to a method of forming an element isolation area including a method of forming a refractory metal silicide film on a diffusion layer of a CMOS transistor in a self aligning manner.
2. Description of the Related Art
Extensive investigations are still being conducted for reducing the size of semiconductor devices and for providing denser packaging. Currently, very large-scale integrated semiconductor devices such as memory devices and logic devices designed with a feature size as narrow as 0.15 to 0.25 micron are being manufactured.
As the integration of semiconductor devices increases, reducing the dimensions of diffusion layer widths and the film thickness of materials constituting semiconductor devices becomes increasingly important. However, this reduction inevitably results in an increase in the wiring resistance of the diffusion layers and electrode materials, which significantly affects the circuit delay.
Therefore, a resistance lowering technology using a refractory metal silicide is essential for manufacturing microscopic semiconductor devices. Especially, silicide (self-align-silicide) technology using a titanium alloy for the refractory metal is important for manufacturing a microscopic insulation gate field effect transistor (hereinafter referred to as a MOS transistor).
In addition, in MOS transistors having the above-described structure, the diffusion of impurities forming the diffusion layer must be suppressed as semiconductor integration continues to increase, to thereby suppress the transistor short channel effect.
Consequently, if the junction face of the diffusion layer contacts the silicide area layer, crystalline defect leakage current increases to disable the transistor switching operation. Therefore, the silicide layer must be made thinner as the junction of the diffusion layer becomes shallower.
FIGS. 9(A)-9(C) through 12(A)-12(B) show cross sections sequentially illustrating prior-art manufacturing processes for MOS transistors having a silicide structure.
First, as shown in FIG. 9(A), a silicon oxide film 302 is formed on the main surface of a silicon substrate 301, and a silicon nitride film 303 is formed on the silicon oxide film 302.
Next, as shown in FIG. 9(B), a resist 304 is patterned by a general lithography technique to open an element isolation area.
As shown in FIG. 9(C), the silicon nitride film 303, the silicon oxide film 302 and the silicon substrate 301 are selectively etched by a dry etching technique.
As shown in FIG. 10(A), the resist is removed and then the silicon substrate 301 is oxidized by heat treating in an H.sub.2 O.sub.2 atmosphere to form a field oxide film 305.
As shown in FIG. 10(B), the silicon nitride film 303 and the silicon oxide film 302 are removed by wet etching. Then, a gate oxide film 307 is formed, a polysilicon film is formed, and the polysilicon is patterned to form a polysilicon gate electrode 308 in this order.
Next, after forming a silicon nitride film, the silicon nitride film is anisotropically etched to form a sidewall spacer 309.
Then, as shown in FIG. 10(C), those portions on which a P-channel MOS transistor is to be formed are coated with a resist 306A. Those portions on which an N-channel MOS transistor is to be formed are ion-implanted with arsenic 311 to form N.sup.+ diffusion layers 312 on the silicon substrate. This diffusion layer provides the source and drain of the N-channel MOS transistor by subsequently applying an activating heat treatment. It should be noted that the black dots in FIGS. 10(C) through 11(C) denote arsenic introduced into the field silicon oxide film 305 by ion implantation.
As shown in FIG. 11(A), the portion on which the N-channel MOS transistor is formed is coated with a resist 306B, and the portion on which the P-channel MOS transistor is formed is ion-implanted with boron (BF.sub.2) 313 to form P.sup.+ diffusion layers 314 on the silicon substrate. This diffusion layer provides the source and drain of the P-channel MOS transistor by a subsequently applied activating heat treatment. Namely, after removing the resist, the P.sup.+ diffusion layers 314 are formed by heat treating at a temperature of from 800 to 1000 degrees centigrade.
Thus, as shown in FIG. 11(B), if the MOS transistor is an N-channel type, the N.sup.+ diffusion layers 312 containing arsenic are formed, and, if the MOS transistor is a P-channel type, the P.sup.+ diffusion layers 314 containing boron are formed, to provide the source and drain of the transistors, respectively.
Then, as shown in FIG. 11(C), a titanium film 315 about 50 nm thick is formed over the whole surface of the wafer by metal sputtering or the like.
After the process of FIG. 11(C), the silicon substrate is heat-treated (the first heat treatment) in a nitrogen atmosphere at atmospheric pressure for 30 to 60 seconds.
Generally, a lamp annealing apparatus is used for the heat treatment, and the heat treatment temperature is set to from 600 to 650 degrees centigrade. Thus, a titanium silicide is formed. A C49-structure silicide layer 316 having a crystalline structure and a high electrical specific resistance of about 60 .mu..OMEGA..multidot.cm and a titanium nitride layer 317 are formed on the exposed surface of the gate electrode polysilicon 308 and the surfaces of the N.sup.+ diffusion layer 312 and the P.sup.+ diffusion layer 314, respectively.
The above-mentioned state is shown only with respect to the P-channel MOS transistor in FIG. 12(A).
Next, the titanium nitride layer 317 is removed by a liquid chemical obtained by mixing an ammoniacal solution, pure water and hydrogen peroxide water. Thus, the C49 structure silicide layer 316 is formed only on the gate electrode polysilicon and the N.sup.+ diffusion layers and the P.sup.+ diffusion layers forming the source/drain areas.
Furthermore, a second heat treatment is performed in a nitrogen atmosphere at atmospheric pressure for about 60 seconds. The lamp annealing apparatus mentioned above is used for the heat treatment apparatus, and the processing temperature is set to about 850 degrees centigrade. By this processing, the above-mentioned C49 structure silicide layer 316 is changed to a C54 structure silicide layer 318 having a crystalline structure having a low electrical specific resistance of about 20 .mu..OMEGA..multidot.cm.
This state is shown only with respect to the P-channel MOS transistor in FIG. 12(B) as in FIG. 12(A).
Then, an interlayer film is formed by growing an oxide film, and lithographic processing and oxide film etching are carried out to expose contacts. A metal such as aluminum is sputtered thereon, and lithographic processing and etching are carried out again, to thereby form an aluminum wiring.
Thus, in the above-mentioned prior-art technology, an undesired C49 silicide structure 316R (FIG. 12(A)) is formed on the silicon oxide film 305 in the field area by the silicide reaction due to the reaction between silicon and titanium and the reduction of the silicon oxide film during heat treatment (the first heat treatment) of the titanium film 315 in a nitrogen atmosphere. This leads to an undesired C54 silicide structure 318R (FIG. 12(B)), resulting in an undesired short circuit path between the P.sup.+ diffusion layers 314 of different MOS transistors. This problem is described in further detail as follows.
Generally, the silicide reaction is suppressed to a greater extent as the impurity density increases. Therefore, the temperature of the first heat treatment used in forming the silicide must be increased to activate the reaction.
FIG. 13 shows the sheet resistance as a function of heat treatment temperature. At heat treatment temperatures 700 degrees centigrade or higher, the resistance of the silicide can be decreased. On the other hand, at these temperatures, a reaction with the silicon oxide film occurs.
FIG. 14 shows the decrease in silicon oxide film thickness as a function of the first heat treatment temperature due to reduction of the silicon oxide film by the titanium film.
FIG. 14 represents data including as parameters the wet etching time after forming the silicide by the first heat treatment and the presence or absence of the heat treatment (the second heat treatment) for the phase transition from a C49 structure to a C54 structure. In FIG. 14, the black triangle, square and circle symbols are associated with the P-channel MOS transistor (P.sub.ch), while the white triangle, square and circle symbols are associated with the N-channel MOS transistor (N.sub.ch).
As the heat treatment temperature is increased, the film thickness of the silicon oxide film is reduced to a greater extent. Especially, there is a large reduction in the thickness of a silicon oxide film that is implanted with boron. This is because the implanted boron promotes a reaction which reduces the thickness of the silicon oxide film, to thereby decrease the thickness of the oxide film involved in the silicide reaction and form a silicide on the silicon oxide film.
This gives rise to the problem of forming a short circuit path along the silicide film which spans the diffusion layers in the silicide forming process of a P-channel MOS transistor.